(a) Field of the Invention
The present invention relates to a wiring board and a method of manufacturing the same. More specifically, the invention relates to a wiring board having a structure in which terminals (pads) for mounting a semiconductor element (chip) or the like or for external connection are exposed from an outermost insulating layer, and also to a method of manufacturing the same.
In the description below, the wiring board is also referred to as a “semiconductor package” for the sake of convenience.
(b) Description of the Related Art
In a trend to make semiconductor devices smaller (thinner) in size and higher in performance (function), there is a demand for package-on-package (POP) bonding for the purpose of reducing the mounting area of a semiconductor device in which electronic components such as semiconductor chips are mounted on wiring boards (in semiconductor packages). In the POP bonding, packages each including a semiconductor chip or the like mounted thereon are stacked in the vertical direction (height direction) thereof.
As one of methods of implementing the POP bonding, there is a method in which upper and lower packages are bonded to each other with an interposer placed therebetween. With this method, a semiconductor device is formed with a structure in which: a semiconductor chip is flip-chip bonded to the lower package (wiring board); terminals (pads) of the lower package are formed in a peripheral region of the chip on the lower package; terminals (pads) of an upper package (wiring board) are formed on the mounting surface side of the upper package in a region corresponding to the peripheral region; and the terminals of the lower and upper packages are bonded to each other via external terminals formed on both surfaces of an interposer having a thickness larger than that of the chip (inclusive of the electrode terminals thereof).
According to the bonding method, a process for fabricating the interposer is required additionally. The typical process for the fabrication includes the steps of: preparing a core member; forming through holes at required positions of the core member; filling the through holes with a conductor; forming resist layers on both surfaces; forming wiring layers in a required pattern in connection with the conductor; removing the resist layers; forming insulating layers (solder resist layers) through which external terminal formation portions of the wiring layer are exposed; and performing a required plating (nickel/gold plating or the like) on the external terminal formation portions.
In addition, as another method of implementing the above POP bonding, there is a method in which terminals (pads) of upper and lower packages are bonded to each other using solder. With this method, a semiconductor device is formed with a structure in which: a semiconductor chip is flip-chip bonded to the lower package (wiring board); and terminals (pads) formed in a peripheral region of the chip on the lower package are bonded via solder bumps to terminals (pads) formed on the mounting surface side of the upper package (wiring board) in a region corresponding to the peripheral region on the lower package.
An example of the techniques related to the above POP bonding is described in Japanese unexamined Patent Publication (JPP) (Kokai) 2008-16819. This publication discloses a bottom board (wiring board) of package-on-package structure which is electrically connected to a top board (wiring board) by solder balls. The bottom board includes a core board, pads formed on the surface of the core board corresponding to the positions of the solder balls, insulating layers stacked on the core board, through holes formed by removing portions of the insulating layers so that the pads are exposed, and a metal layer formed by filling the through holes and electrically connected to the solder balls.
As described above, in the conventional techniques, connection using an interposer or solder is performed for implementing POP bonding. However, in the case where an interposer is used for bonding, there arises a problem in that another process (considerable manufacturing steps) for fabricating the interposer is required, and a material for fabricating the interposer is required as well, to thus increase the manufacturing cost.
On the other hand, in the case where solder is used for bonding, the gap between the upper and lower packages is large because of the presence of the chip mounted between the packages. Accordingly, a large amount of solder (bump) is used for bonding the packages together. In this case, there are inconveniences such as separation of the bump (solder) during reflow soldering, and formation of a bridge between adjacent bumps. This leads to a problem in that the reliability of bonding between the upper and lower packages decreases.
In addition, because of the presence of the chip mounted between the upper and lower packages, both of the above bonding methods have another problem in that, where the chip has a large thickness, the whole POP structure cannot be constructed as small and thin as desired.